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for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 1 HMCAD1041-40 v01.0411 single 10-bit 20/ 40 msps a/d converter functional diagram features ? 10-bit resolution ? 20/40 m s p s maximum sampling rate ? ultra-low power dissipation: 15/25 mw ? 61.6 db snr @ 8 mhz fi n ? internal reference circuitry ? 1.8 v core supply voltage ? 1.7 - 3.6 v i/ o supply voltage ? parallel cm os output ? 6 x 6 mm 40-pin qf n (lp6h e ) package t ypical applications ? medical imaging ? portable t est e quipment ? digital o scilloscopes ? if communication g eneral description t he HMCAD1041-40 is a high performance ultra low power analog-to-digital converter (adc). t he adc employs internal reference circuitry, a cm os control interface, cm os output data and is based on a proprietary structure. digital error correction is employed to ensure no missing codes in the complete full scale range. t wo idle modes with fast startup times exist. t he entire chip can either be put in s tandby mode or power down mode. t he two modes are optimized to allow the user to select the mode resulting in the lowest possible energy consumption during idle mode and startup. t he HMCAD1041-40 has a highly linear t ha optim- ized for frequencies up to n yquist. t he differential clock interface is optimized for low jitter clock sources and supports l v d s , l v p e cl, sine wave and cm os clock inputs. pin compatible with hmcad1041-80, hmcad1051-40 and hmcad1051-80. figure 1. functional block diagram
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 2 HMCAD1041-40 v01.0411 single 10-bit 20/ 40 msps a/d converter e lectrical specifcations dc e lectrical specifcations a v dd= 1.8v , d v dd= 1.8v , d v ddck= 1.8v , ov dd= 2.5 v , 20/40 m sps clock, 50% clock duty cycle, -1 dbfs 8 mhz input signal, unless otherwise noted parameter condition min typ max unit dc accuracy no missing codes guaranteed o ffset error midscale offset 1 l sb gain error full scale range deviation from typical 6 %fs dnl differential nonlinearity 0.15 l sb inl integral nonlinearity 0.2 l sb v cm common mode voltage output v a vdd /2 v analog input input common mode analog input common mode voltage v cm -0.1 v cm +0.2 v full scale range differential input voltage range 2 vpp input capacitance differential input capacitance 2 pf bandwidth input bandwidth 500 mhz power supply core s upply v oltage s upply voltage to all 1.8v domain pins. s ee pin confguration and description 1.7 1.8 2 v i/o s upply v oltage o utput driver supply voltage ( ov dd). should be higher than or equal to core s upply v oltage ( v ov dd v d vdd ) 1.7 2.5 3.6 v
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 3 HMCAD1041-40 v01.0411 single 10-bit 20/ 40 msps a/d converter ac e lectrical specifcations - 20 msps a v dd=1.8v , d v dd=1.8v , d v ddck=1.8v , ovdd=2.5v , fs=20msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, unless otherwise noted. parameter condition min typ max unit performance snr s ignal to noise r atio f in = 2 mhz 61.7 dbfs f in = 8 mhz 60 61.6 dbfs f in =~ fs/2 61.6 dbfs f in = 20 mhz 61.6 dbfs sndr s ignal to n oise and distortion r atio f in = 2 mhz 61.7 dbfs f in = 8 mhz 60 61.6 dbfs f in =~ fs/2 60.5 dbfs f in = 20 mhz 61.6 dbfs sfdr s purious free dynamic r ange f in = 2 mhz 80 dbc f in = 8 mhz 70 81 dbc f in =~ fs/2 70 dbc f in = 20 mhz 80 dbc hd2 s econd order harmonic distortion f in = 2 mhz -90 dbc f in = 8 mhz -80 -90 dbc f in =~ fs/2 -90 dbc f in = 20 mhz -90 dbc hd3 t hird order harmonic distortion f in = 2 mhz -80 dbc f in = 8 mhz -70 -81 dbc f in =~ fs/2 -70 dbc f in = 20 mhz -80 dbc enob e ffective number of bits f in = 2 mhz 10 bits f in = 8 mhz 9.7 9.9 bits f in =~ fs/2 9.8 bits f in = 20 mhz 9.9 bits power supply analog supply current 5.7 ma digital supply current digital core supply 1 ma o utput driver supply 2.5v output driver supply, sine wave input, f in = 1 mhz, ck_ext enabled 1.7 ma o utput driver supply 2.5v output driver supply, sine wave input, f in = 1 mhz, ck_ext disabled 1.2 ma analog power dissipation 10.3 mw digital power dissipation ov dd = 2.5v , 5pf load on output bits, f in = 1 mhz, ck_ext disabled 4.8 mw t otal power dissipation ov dd = 2.5v , 5pf load on output bits, f in = 1 mhz, ck_ext disabled 15.1 mw power down dissipation 9.9 w sleep mode power dissipation, sleep mode 7.7 mw clock inputs max. conversion r ate 20 msps min. conversion r ate 3 msps
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 4 HMCAD1041-40 v01.0411 single 10-bit 20/ 40 msps a/d converter ac e lectrical specifcations - 40 msps a v dd=1.8v , d v dd=1.8v , d v ddck=1.8v , ovdd=2.5v , fs=40msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, unless otherwise noted. parameter condition min typ max unit performance snr s ignal to n oise r atio f i n = 2 mhz 61.6 dbf s f i n = 8 mhz 60 61.6 dbf s f i n =~ fs /2 61.6 dbf s f i n = 30 mhz 61.5 dbf s sn d r s ignal to n oise and distortion r atio f i n = 2 mhz 61.6 dbf s f i n = 8 mhz 60 61.6 dbf s f i n =~ fs /2 61.2 dbf s f i n = 30 mhz 61.4 dbf s s fd r s purious free dynamic r ange f i n = 2 mhz 80 dbc f i n = 8 mhz 70 81 dbc f i n =~ fs /2 72 dbc f i n = 30 mhz 80 dbc hd2 s econd order harmonic distortion f i n = 2 mhz -90 dbc f i n = 8 mhz -80 -90 dbc f i n =~ fs /2 -85 dbc f i n = 30 mhz -85 dbc hd3 t hird order harmonic distortion f i n = 2 mhz -80 dbc f i n = 8 mhz -70 -81 dbc f i n =~ fs /2 -72 dbc f i n = 30 mhz -80 dbc eno b e ffective number of bits f i n = 2 mhz 9.9 bits f i n = 8 mhz 9.7 9.9 bits f i n =~ fs /2 9.9 bits f i n = 30 mhz 9.9 bits power supply analog supply current 9.3 ma digital supply current digital core supply 1.7 ma o utput driver supply 2.5 v output driver supply, sine wave input, f i n = 1 mhz, ck_ e x t enabled 3.1 ma o utput driver supply 2.5 v output driver supply, sine wave input, f i n = 1 mhz, ck_ e x t disabled 2.2 ma analog power dissipation 16.7 mw digital power dissipation ov dd = 2.5 v , 5pf load on output bits, f i n = 1 mhz, ck_ e x t disabled 8.6 mw t otal power dissipation ov dd = 2.5 v , 5pf load on output bits, f i n = 1 mhz, ck_ e x t disabled 25.3 mw power down dissipation 9.7 w s leep mode power dissipation, s leep mode 11.3 mw clock inputs max. conversion r ate 40 m s p s min. conversion r ate 3 m s p s
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 5 HMCAD1041-40 v01.0411 single 10-bit 20/ 40 msps a/d converter digital and t iming specifcations a v dd=1.8v , d v dd=1.8v , d v ddck=1.8v , ovdd=2.5v , conversion r ate: max specifed, 50% clock duty cycle, -1dbf s input signal, 5 pf capacitive load on data outputs, unless otherwise noted parameter condition min typ max unit clock inputs duty cycle 20 80 % high compliance cmos , l vds , l vpecl, s ine wave input range differential input swing 0.4 vpp input range differential input swing, sine wave clock input 1.6 vpp input common mode voltage keep voltages within ground and voltage of ov dd 0.3 v ov dd -0.3 v input capacitance differential 2 pf timing t pd s tart up time from power down mode to active mode 900 clock cycles t slp s tart up time from s leep mode to active mode 20 clock cylcles t ovr o ut of range recovery time 1 clock cycles t ap aperture delay 0.8 ns ?rms aperture jitter < 0.5 ps t la t pipeline delay 12 clock cycles t d o utput delay (see timing diagram). 5pf load on output bits 3 10 ns t dc o utput delay relative to ck_ext (see timing diagram) 1 6 ns logic inputs v hi high level input v oltage. v ov dd 3.0v 2 v v hi high level input v oltage. v ov dd = 1.7 v C 3.0v 0.8 v ov dd v v li low level input v oltage. v ov dd 3.0v 0 0.8 v v li low level input v oltage. v ov dd = 1.7 v C 3.0v 0 0.2 v ov dd v i hi high level input leakage current 10 a i li low level input leakage current 10 a c i input capacitance 3 pf logic outputs v ho high level output v oltage v ov dd -0.1 v v l o low level output v oltage 0.1 v c l max capacitive load. post-driver supply voltage equal to pre-driver supply voltage v ov dd = v ocvdd 5 pf c l max capacitive load. post-driver supply voltage above 2.25 v (1) 10 pf (1) t he outputs will be functional with higher loads. however, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents and resulting switching noise at a minimum
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 6 HMCAD1041-40 v01.0411 single 10-bit 20/ 40 msps a/d converter t iming diagram figure 2: t iming diagram absolute maximum r atings absolute maximum ratings are limiting values to be applied for short periods of time. e xposure to absolute maxi - mum rating conditions for an extended period of time may reduce device lifetime. t able 1: pin pin rating a vdd vss -0.3v to +2.3v d vdd vss -0.3v to +2.3v a vss , d vssck, d vss , ovss vss -0.3v to +0.3v ov dd vss -0.3v to +3.9v ip, i n, analog inputs and outputs vss -0.3v to +2.3v digital outputs vss -0.3v to +3.9v ckp, ck n vss -0.3v to +3.9v digital inputs vss -0.3v to +3.9v o perating temperature -40 to +85 oc s torage temperature -60 to +150 oc s oldering profle qualifcation j- std-020 e l e c trost a t ic sens i t i ve d ev ic e o b serve ha n dli n g p re cau t i ons s tresses above those listed under absolute maximum r atings may cause permanent damage to the device. t his is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. e xposure to absolute maximum rating conditions for extended periods may affect device reliability.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 7 HMCAD1041-40 v01.0411 single 10-bit 20/ 40 msps a/d converter pin confguration and description figure 3: package drawing, qf n 40-pin
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 8 HMCAD1041-40 v01.0411 single 10-bit 20/ 40 msps a/d converter t able 2: pin function pin # name description 0 vss ground connection for all power domains. e xposed pad 1, 11, 16 d v dd digital and i/ o -ring pre driver supply voltage, 1.8 v 2 cm_ e x t common mode voltage output 3, 4, 7, a v dd analog supply voltage, 1.8 v 5, 6 ip, i n analog input (non-inverting, inverting) 8 d v ddck clock circuitry supply voltage, 1.8 v 9 ckp clock input, non-inverting (format: l v d s , l v p e cl, cm os / tt l, s ine wave) 10 ck n clock input, inverting. for cm os input on ckp, connect ck n to ground. 12 ck_ e x t _ en ck_ e x t signal enabled when low (zero). t ristate when high. 13 df r m t data format selection. 0: o ffset binary, 1: t wos complement 14 pd_ n full chip power down mode when low. all digital outputs reset to zero. after chip power up always apply power down mode before using active mode to reset chip. 15 oe _ n o utput e nable. t ristate when high 17, 18, 25, 26, 36, 37 ov dd i/ o ring post-driver supply voltage. v oltage range 1.7 to 3.6 v 19 n c 20 n c 21 n c 22 d_0 o utput data (l s b) 23 d_1 o utput data 24 orn g o ut of r ange fag. high when input signal is out of range 27 ck_ e x t o utput clock signal for data synchronization. cm os levels 28 d_2 o utput data 29 d_3 o utput data 30 d_4 o utput data 31 d_5 o utput data 32 d_6 o utput data 33 d_7 o utput data 34 d_8 o utput data 35 d_9 o utput data (m s b) 38, 39 cm_ e x t bc_1, cm_ e x t bc_0 bias control bits for the buffer driving pin cm_ e x t 00: o ff 01: 50ua 10: 500ua 11: 1ma 40 s lp_ n s leep mode when low
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 9 HMCAD1041-40 v01.0411 single 10-bit 20/ 40 msps a/d converter r ecommended usage analog input t he analog inputs to the HMCAD1041-40 is a switched capacitor track-and-hold amplifer optimized for differ - ential operation. o peration at common mode voltages at mid supply is recommended even if performance will be good for the ranges specifed. t he cm_ e x t pin provides a voltage suitable as common mode voltage reference. t he internal buffer for the cm_ e x t voltage can be switched off, and driving capabilities can be changed by using the cm_ e x t bc control input. figure 4 shows a simplifed drawing of the input net - work. t he signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. a small external resistor (e.g. 22 o hm) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. a small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve perfor - mance. t he resistors form a low pass flter with the capacitor, and values must therefore be determined by requirements for the application. figure 4: input confguration dc-coupling figure 5 shows a recommended confguration for dc- coupling. n ote that the common mode input voltage must be controlled according to specifed values. pref - erably, the cm_ e x t output should be used as refer - ence to set the common mode voltage. figure 5: dc coupled input with buffer t he input amplifer could be inside a companion chip or it could be a dedicated amplifer. s everal suitable single ended to differential driver amplifers exist in the market. t he system designer should make sure the specifcations of the selected amplifer is adequate for the total system, and that driving capabilities comply with the HMCAD1041-40 input specifcations. detailed confguration and usage instructions must be found in the documentation of the selected driver, and the values given in fgure 5 must be varied according to the recommendations for the driver. ac-coupling a signal transformer or series capacitors can be used to make an ac-coupled input network. figure 6 shows a recommended confguration using a transformer. make sure that a transformer with sufficient linearity is selected, and that the bandwidth of the transformer is appropriate. t he bandwidth should exceed the sam - pling rate of the adc with at least a factor of 10. it is also important to minimize phase mismatch between the differential adc inputs for good hd2 performance. t his type of transformer coupled input is the preferred confguration for high frequency signals as most differ - ential amplifers do not have adequate performance at high frequencies. if the input signal is traveling a long physical distance from the signal source to the trans - former (for example a long cable), kick-backs from the adc will also travel along this distance. if these kick- backs are not terminated properly at the source side, they are refected and will add to the input signal at the adc input. t his could reduce the adc performance. t o avoid this effect, the source must effectively ter - minate the adc kick-backs, or the traveling distance should be very short. if this problem could not be avoided, the circuit in fgure 8 can be used.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 10 HMCAD1041-40 v01.0411 single 10-bit 20/ 40 msps a/d converter figure 6: t ransformer coupled input figure 7 shows ac-coupling using capacitors. r esis - tors from the cm_ e x t output, r cm, should be used to bias the differential input signals to the correct volt - age. t he series capacitor, ci, form the high-pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. figure 7: ac coupled input n ote that startup time from s leep mode and power down mode will be affected by this flter as the time required to charge the series capacitors is dependent on the flter cut-off frequency. if the input signal has a long traveling distance, and the kick-backs from the adc not are effectively terminated at the signal source, the input network of fgure 8 can be used. t he confguration in fgure 8 is designed to attenuate the kickback from the adc and to provide an input impedance that looks as resistive as possible for frequencies below n yquist. v alues of the series inductor will however depend on board design and conversion rate. in some instances a shunt capaci - tor in parallel with the termination resistor (e.g. 33pf) may improve adc performance further. t his capacitor attenuate the adc kick-back even more, and minimize the kicks traveling towards the source. however, the impedance match seen into the transformer becomes worse. figure 8: alternative input network clock input and jitter considerations t ypically high-speed adcs use both clock edges to generate internal timing signals. in the hmcad1041- 40 only the rising edge of the clock is used. hence, input clock duty cycles between 20% and 80% are acceptable. t he input clock can be supplied in a variety of formats. t he clock pins are ac-coupled internally. hence a wide common mode voltage range is accepted. differ - ential clock sources as l v d s , l v p e cl or differential sine wave can be connected directly to the input pins. for cm os inputs, the ck n pin should be connected to ground, and the cm os clock signal should be con - nected to ckp. for differential sine wave clock, the input amplitude must be at least 800 m v pp. t he quality of the input clock is extremely important for high-speed, high-resolution adcs. t he contribu - tion to snr from clock jitter with a full scale signal at a given frequency is shown in equation 1, snr jitter = 20 log (2 ? in ? t ) (1) where fi n is the signal frequency, and t is the total rms jitter measured in seconds. t he rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal adc circuitry. for applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. t his can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifcations) and make sure the clock dis - tribution is well controlled. it might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. it is of utmost importance to avoid cross - talk between the adc output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. t he jitter performance is improved with reduced rise and fall times of the input clock. hence, optimum jitter performance is obtained with l v d s or l v p e cl clock with fast edges. cm os and sine wave clock inputs will result in slightly degraded jitter performance.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 11 HMCAD1041-40 v01.0411 single 10-bit 20/ 40 msps a/d converter if the clock is generated by other circuitry, it should be re-timed with a low jitter master clock as the last operation before it is applied to the adc clock input. digital outputs digital output data are presented on parallel cm os form. t he voltage on the ov dd pin set the levels of the cm os outputs. t he output drivers are dimensioned to drive a wide range of loads for ov dd above 2.25 v , but it is recommended to minimize the load to ensure as low transient switching currents and resulting noise as possible. in applications with a large fanout or large capacitive loads, it is recommended to add external buffers located close to the adc chip. t he timing is described in the t iming diagram section. n ote that the load or equivalent delay on ck_ e x t always should be lower than the load on data outputs to ensure sufficient timing margins. t he digital outputs can be set in tristate mode by set - ting the oe _ n signal high. t he HMCAD1041-40 employs digital offset correc - tion. t his means that the output code will be 4096 with shorted inputs. however, small mismatches in para - sitics at the input can cause this to alter slightly. t he offset correction also results in possible loss of codes at the edges of the full scale range. with no offset correction, the adc would clip in one end before the other, in practice resulting in code loss at the oppo - site end. with the output being centered digitally, the output will clip, and the out of range fags will be set, before max code is reached. when out of range fags are set, the code is forced to all ones for overrange and all zeros for underrange. data format selection t he output data are presented on offset binary form when df r m t is low (connect to ovss ). s etting df r m t high (connect to ov dd) results in 2s comple - ment output format. details are shown in table 3. t able 3: data format description for 2 v pp full scale r ange differential input voltage (ip - in) output data: d_9 : d_0 (df r m t = 0, o ffset binary ) output data: d_9 : d_0 (df r m t = 1, 2s complement) 1.0 v 11 1111 1111 01 1111 1111 +0.24m v 10 0000 0000 00 0000 0000 -0.24m v 01 1111 1111 11 1111 1111 -1.0 v 00 0000 0000 10 0000 0000 reference voltages t he reference voltages are internally generated and buffered based on a bandgap voltage reference. n o external decoupling is necessary, and the reference voltages are not available externally. t his simplifes usage of the adc since two extremely sensitive pins, otherwise needed, are removed from the interface. operational modes t he operational modes are controlled with the pd_ n and s lp_ n pins. if pd_ n is set low, all other control pins are overridden and the chip is set in power down mode. in this mode all circuitry is completely turned off and the internal clock is disabled. hence, only leak - age current contributes to the power down dissipa - tion. t he startup time from this mode is longer than for s leep mode as all references need to settle to their fnal values before normal operation can resume. t he s lp_ n signal can be used to set the full chip in s leep mode. in this mode internal clocking is disabled, but some low bandwidth circuitry is kept on to allow for a short startup time. however, s leep mode represents a signifcant reduction in supply current, and it can be used to save power even for short idle periods. t he input clock should be kept running in all idle modes. however, even lower power dissipation is pos - sible in power down mode if the input clock is stopped. in this case it is important to start the input clock prior to enabling active mode. startup initialization t he HMCAD1041-40 must be reset prior to normal operation. t his is required every time the power supply voltage has been switched off. a reset is per - formed by applying power down mode. wait until a stable supply voltage has been reached, and pull the pd_ n pin for the duration of at least one clock cycle. t he input clock must be running continuously during this power down period and until active operation is reached. alternatively the pd pin can be kept low during power-up, and then be set high when the power supply voltage is stable.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 12 HMCAD1041-40 v01.0411 single 10-bit 20/ 40 msps a/d converter o utline drawing t able 4: 6x6 mm qfn (40 pin lp6h) dimensions symbol millimeter inch min typ max min typ max a 0.9 0.035 a1 0 0.01 0.05 0 0.000 0.002 a2 0.65 0.7 0.026 0.028 a3 0.2 ref 0.008 ref b 0.2 0.25 0.32 0.008 0.01 0.013 d 6.00 bsc 0.236 bsc d1 5.75 bsc 0.226 bsc d2 3.95 4.1 4.25 0.156 0.162 0.167 l 0.3 0.4 0.5 0.012 0.016 0.02 e 0.50 bsc 0.020 bsc 1 0 12 0 12 f 0.2 0.008 g 0.24 0.42 0.6 0.010 0.017 0.024 package i nformation part number package body material lead finish msl [1] package marking [2] HMCAD1041-40 r oh s -compliant low s tress injection molded plastic 100% matte s n level 2a a s d0401 xxxx xxxx [1] m s l, peak t emp: t he moisture sensitivity level rating classifed according to the j e d e c industry standard and to peak solder temperature. [2] proprietary marking xxxx, 4-digit lot number xxxx

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